From be2bf6f47b6e3984037dae755f0b649c50ba1970 Mon Sep 17 00:00:00 2001 From: Jan Siwiec <jan.siwiec@vsb.cz> Date: Thu, 15 Feb 2024 09:13:04 +0100 Subject: [PATCH] Update 5 files - /docs.it4i/cs/specifications.md - /docs.it4i/cs/introduction.md - /docs.it4i/cs/guides/xilinx.md - /docs.it4i/cs/guides/horizon.md - /mkdocs.yml --- docs.it4i/cs/guides/horizon.md | 2 +- docs.it4i/cs/guides/xilinx.md | 2 +- docs.it4i/cs/introduction.md | 1 + docs.it4i/cs/specifications.md | 17 +++++++++++++++++ mkdocs.yml | 1 + 5 files changed, 21 insertions(+), 2 deletions(-) diff --git a/docs.it4i/cs/guides/horizon.md b/docs.it4i/cs/guides/horizon.md index 2d602cf7c..078b79e6f 100644 --- a/docs.it4i/cs/guides/horizon.md +++ b/docs.it4i/cs/guides/horizon.md @@ -1,4 +1,4 @@ -# VMware Horizon +# Using VMware Horizon VMware Horizon is a virtual desktop infrastructure (VDI) solution that enables users to access virtual desktops and applications from any device and any location. diff --git a/docs.it4i/cs/guides/xilinx.md b/docs.it4i/cs/guides/xilinx.md index 661e58eaa..8611bd280 100644 --- a/docs.it4i/cs/guides/xilinx.md +++ b/docs.it4i/cs/guides/xilinx.md @@ -1,4 +1,4 @@ -# Xilinx Accelerator Platform +# Using Xilinx Accelerator Platform The first step to use Xilinx accelerators is to initialize Vitis (compiler) and XRT (runtime) environments. diff --git a/docs.it4i/cs/introduction.md b/docs.it4i/cs/introduction.md index 4edb6a4f4..d3b85037a 100644 --- a/docs.it4i/cs/introduction.md +++ b/docs.it4i/cs/introduction.md @@ -27,6 +27,7 @@ Second stage of complementary systems implementation comprises of these partitio - compute partition 8 - modern CPU with a very high L3 cache capacity (over 750MB) - compute partition 9 - virtual GPU accelerated workstations - compute partition 10 - Sapphire Rapids-HBM server +- compute partition 11 - NVIDIA Grace CPU Superchip  diff --git a/docs.it4i/cs/specifications.md b/docs.it4i/cs/specifications.md index d89d69c2a..d7df32455 100644 --- a/docs.it4i/cs/specifications.md +++ b/docs.it4i/cs/specifications.md @@ -214,7 +214,24 @@ The server is also equipped with DDR5 memory and enables the comparative studies - 2x Intel D3 S4520 960GB SATA 6Gb/s - 1x Supermicro Standard LP 2-port 10GbE RJ45, Broadcom BCM57416 +## Partition 11 - NVIDIA Grace CPU Superchip + +The [NVIDIA Grace CPU Superchip][6] uses the [NVIDIA® NVLink®-C2C][5] technology to deliver 144 Arm® Neoverse V2 cores and 1TB/s of memory bandwidth. +Runs all NVIDIA software stacks and platforms, including NVIDIA RTX™, NVIDIA HPC SDK, NVIDIA AI, and NVIDIA Omniverse™. + + +- Superchip design with up to 144 Arm Neoverse V2 CPU cores with Scalable Vector Extensions (SVE2) +- World’s first LPDDR5X with error-correcting code (ECC) memory, 1TB/s total bandwidth +- 900GB/s coherent interface, 7X faster than PCIe Gen 5 +- NVIDIA Scalable Coherency Fabric with 3.2TB/s of aggregate bisectional bandwidth +- 2X the packaging density of DIMM-based solutions +- 2X the performance per watt of today’s leading CPU +- FP64 Peak of 7.1TFLOPS + [1]: https://www.bittware.com/fpga/520n-mx/ [2]: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#overview [3]: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html#overview [4]: https://developer.arm.com/documentation/100095/0003/ +[5]: https://www.nvidia.com/en-us/data-center/nvlink-c2c/ +[6]: https://www.nvidia.com/en-us/data-center/grace-cpu-superchip/ + diff --git a/mkdocs.yml b/mkdocs.yml index a7b0ae559..0f9c23a00 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -150,6 +150,7 @@ nav: - Specification: cs/specifications.md - Complementary System Job Scheduling: cs/job-scheduling.md - Guides: + - NVIDIA Grace Partition: cs/guides/grace.md - IBM Power10 Partition: cs/guides/power10.md - AMD Partition: cs/guides/amd.md - ARM Partition: cs/guides/arm.md -- GitLab