Merge branch 'cs-p10' into 'master'

Cs p10

See merge request !453

docs.it4i/cs/introduction.md

@@ -26,6 +26,7 @@ Second stage of complementary systems implementation comprises of these partitio
 - compute partition 7 - based on IBM Power10 architecture
 - compute partition 8 - modern CPU with a very high L3 cache capacity (over 750MB)
 - compute partition 9 - virtual GPU accelerated workstations
+- compute partition 10 - Sapphire Rapids-HBM server
 
 ![](../img/cs2_2.png)
 

docs.it4i/cs/specifications.md

@@ -199,6 +199,22 @@ The following is the list of software available on partiton 09:
 - 40x Windows 10/11 Enterprise E3 VDA (Microsoft) per year
 - Hardware VMware Horizon management
 
+
+## Partition 10 - Sapphire Rapids-HBM Server
+
+The primary purpose of this server is to evaluate the impact of the HBM memory on the x86 processor
+on the performance of the user applications.
+This is a new feature previously available only on the GPGPU accelerators
+and provided a significant boost to the memory-bound applications.
+Users can also compare the impact of the HBM memory with the impact of the large L3 cache
+available on the AMD Milan-X processor also available on the complementary systems.
+The server is also equipped with DDR5 memory and enables the comparative studies with reference to DDR4 based systems.
+
+- 2x Intel® Xeon® CPU Max 9468 48 cores base 2.1GHz, max 3.5Ghz
+- 16x 16GB DDR5 4800Mhz
+- 2x Intel D3 S4520 960GB SATA 6Gb/s
+- 1x Supermicro Standard LP 2-port 10GbE RJ45, Broadcom BCM57416
+
 [1]: https://www.bittware.com/fpga/520n-mx/
 [2]: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#overview
 [3]: https://www.xilinx.com/products/boards-and-kits/alveo/u280.html#overview